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High-Performance Fractional-N Frequency Synthesizer
ICS8430002
DATA SHEET
General Description
The ICS8430002 is a general purpose, highperformance, fractional-n LVPECL frequency HiPerClockSTM synthesizer which can generate frequencies for a wide variety of applications with output frequency step sizes of <10ppm. The ICS8430002 has a 2:1 input Multiplexer from which either a crystal input or a differential input can be selected. The differential input can be wired to accept single-ended signals (see the applications section of this datasheet).
Features
* * * * * * * * *
6-Bit Integer and 12-Bit Fractional Feedback Divider Dual differential 3.3V LVPECL outputs which can be set independently for either 3.3V or 2.5V 2:1 Input Mux: One differential input One crystal oscillator interface PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL Output frequency range: 30.625MHz to 640MHz Crystal input frequency range: 12MHz to 40MHz VCO range: 490MHz to 650MHz Parallel or serial interface for programming feedback divider and output dividers Supply voltage modes: Core/Outputs: 3.3V/3.3V 3.3V/2.5V 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package
ICS
Each of the differential LVPECL outputs has an output divider which can be independently set so that two different frequencies can be generated. Additionally, each LVPECL output pair has a dedicated power supply pin so the outputs can run at 3.3V or 2.5V. The ICS8430002 also supplies a buffered copy of the reference clock or crystal frequency on the single-ended REF_OUT pin which can be enabled or disabled (disabled by default). The output frequency can be programmed using either a serial or parallel programming interface. The device features a fractional feedback divider with a 6-bit integer and 12-bit fractional value. The minimum step value of the feedback divider is 1/4096.
* *
Pin Assignment
P1 P0 M5 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD nPCLK PCLK
P2 NB0 NB1 NB2 OE_REF OEA OEB VCC NA0 NA1 NA2 VEE
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 ICS8430002 33 48 Lead LQFP 5 7mm x 7mm x 1.4mm 32 6 31 package body 7 30 8 29 Y Package 9 28 Top View 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4
FOUTA nFOUTA VCCO_A FOUTB nFOUTB VCCO_B REF_OUT VCCO_REF nc TEST VCC VEE
nc nc XTAL_OUT XTAL_IN nc nc SEL VCCA S_LOAD S_DATA S_CLOCK MR
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ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Block Diagram
OEA Pullup VCO_SEL Pullup XTAL_IN OSC XTAL_OUT PCLK Pulldown nPCLK Pullup/Pulldown
Pulldown 3 0 0
000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 /1 /2 /3 /4 FOUTA /5 /6 nFOUTA /8 /16 VCCO_A /1 /2 VCCO_B FOUTB /3 /4 nFOUTB /5 /6 /8 /16
P_DIV
1
Phase Detector
VCO
1
/M SEL P[2:0] Pulldown OEB Pullup MR Pulldown
OE_REF S_LOAD S_DATA S_CLOCK nP_LOAD M5:M0 NA2:NA0 NB2:NB0 Pulldown Pulldown Pulldown Pulldown Pulldown 6 3 3
VCCO_REF
REF_OUT
Configuration Interface Logic
TEST
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ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes the operation using a 25MHz crystal or clock input. Valid PLL loop divider values for different crystal or clock input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1 and NOTE 2. When a crystal is being used, there is no pre-divider therefore set P = 1 when referencing all following equations on this page. The ICS8430002 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. It has a 2:1 multiplexer from which either a crystal input or a differential input can be selected. An external fundamental-mode quartz crystal can be used as the input to the on-chip crystal oscillator. The range of allowable crystal frequencies is 12MHz to 40MHz. When selected, the crystal frequency is the reference frequency input to the phase detector. The relationship between the VCO frequency, the crystal input frequency and the M divider (M) is as follows: F VCO = XTAL x M A differential input clock can also be used. (See the Application Information section for Wiring the Differential Input to Accept Single-Ended Levels.) The differential input is followed by a pre-divider that divides down the clock input frequency. This allows an equal or lower reference frequency for the phase detector. See Table 3C for available pre-divider values. The pre-divider value is set through the P[2:0] pins or by using the serial programming interface. The output frequency of the pre-divider is the reference frequency input to the phase detector. The input frequency range of the phase detector is 9MHz to 50MHz. The relationship between the VCO frequency, the clock input frequency, the pre-divider (P) and the M divider (M) is as follows: F IN F VCO = -------- x M P Using a 25MHz input, the M value integer-only range is shown in Table 3B, Programmable VCO Frequency Table, P = /1. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 19.6 M 25.6. For different reference frequencies, the range of valid M values may be calculated as follows: 490MHz --------------------- M 650MHz --------------------F IN P F IN P The output of the VCO is scaled by output dividers prior to being sent to each of the LVPECL output buffers. The output divider settings and output frequency ranges are shown in table 3D. Combining all the values of input frequency, pre-divider setting, integer and fractional feedback divider settings, and output divider setting, the output frequency may be calculated. The frequency out is defined as follows: F IN M F VCO F OUT = ------------- = -------- x ---P N N The fractional-n M divider is composed of a 6-bit integer portion and a 12-bit fractional portion. The decimal value obtained from these settings can be determined as follows: M FRAC M = M INT + -----------------4096 Where:MINT is the 6-bit integer portion MFRAC is the 12-bit fractional portion For a given required M divider, the value to program into the MFRAC register is calculated by taking the fractional portion and multiplying by 4096. For example, assuming a 25MHz crystal is being used, and the desired VCO frequency is 515.625 (to support ethernet with 64B/66B encoding) the feedback setting required would be 20.625. The integer portion of this number (20) is programed into the MINT register. The fractional portion (0.625) is multiplied by 4096. The result (2560) is programmed into the MFRAC register. The full M divider setting is then: 20 + 2560 = 20.625 ----------4096 The frequency step size in ppm can be calculated using the following: F0 - F1 6 stepsize = ----------------- x 10 ppm F0 F IN M Substituting the combined equation -------- x ---- for the F terms in the P N step size equation, the equation can be reduced to just the change in M values. M0 - M1 6 stepsize = --------------------- x 1 x10 ppm M0
Input Min (MHz) 9 18 36 45 72 144 225 288
Input Max (MHz) 50 100 200 250 400 800 800 800
Pre-Divider /1 /2 /4 /5 /8 /16 /25 /32
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. The VCO of the PLL operates over a range of 490MHz to 650MHz. Note that for some values of M (either too high or too low), the PLL will not achieve lock.
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ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Assuming a 25MHz reference frequency and a VCO frequency of 637.5MHz (which, with an output divider of 6 would give an output frequency of 106.25MHz, a common Fibre channel reference frequency), requires an M setting of 25.5 (the integer portion being 25 and the fractional portion being 2048/4096). If you decrease the fractional portion of the M divider by one bit (from 2048 to 2047), the frequency change in ppm is calculated by:
6 stepsize = ( 25.5 - 25.499755859375 ) x 1 x10 ppm ---------------------------------------------------------------25.5
initially LOW. The data on the M, NA, and NB inputs are passed directly to the M divider and both N output dividers. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M and N dividers remain loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and Nx bits can be hardwired to set the M divider and Nx output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the P pre-divider, M divider and Nx output divider when S_LOAD transitions from LOW-to-HIGH. The P pre-divider, M divider and Nx output divider values are latched on the HIGH-to-LOW transition of S_LOAD. The serial mode can be used to program the P, M and Nx bits and test bits T1 and T0. The data bits are clocked in the following order as in the table below.
Which, for these conditions, is a step size of 9.6 ppm. The ICS8430002 supports either serial or parallel programming modes to program the P pre-divider, M feedback divider and N output divider, however the parallel interface can only program the integer portion of the feedback divider. The fractional portion of the feedback divider must be programmed serially. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is
T1
T0
NB2
NB1
NB0
NA2
NA1
NA0
P2
P1
P0
DS1
DS0
...
MFRAC11
MFRAC10
MFRAC9
MFRAC8
MFRAC7
MFRAC6
MFRAC5
MFRAC4
MFRAC3
MFRAC2
MFRAC1
MFRAC0
...
MINT5
MINT4
MINT3
MINT2
MINT1
MINT0
SERIAL LOADING
S_CLOCK S_DATA
t
S_LOAD nP_LOAD
S
t
H
PARALLEL LOADING
M, N, P
t
S
M[5:0], NX[2:0], P[2:0] nP_LOAD
t
S
t
H
S_LOAD
Time
Figure 1. Parallel & Serial Load Operations
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The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW S_DATA, Shift Register Output Reserved Reserved
The function of the DS1, and DS0 bits is as follows: DS1 0 1 0 1 DS0 0 1 1 0 Function Integer Mode Only Fractional Mode Only Do Not Use Do Not Use
Table 1. Pin Descriptions
Number 1, 47, 48 2, 3 4 5 Name P2, P0, P1 NB0, NB1 NB2 OE_REF Input Input Input Input Type Pulldown Pullup Pulldown Pulldown Description Pre-divider control input pins. See table 3C. LVCMOS/LVTTL interface levels. Determines output divider value as defined in Table 3D, Function Table. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of REF_OUT output. When HIGH, the output is active. When LOW, the output is high-impedance. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of FOUTA, nFOUTA outputs. When HIGH, the outputs are active. When LOW, the true output is low and the compliment output is high. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of FOUTB, nFOUTB outputs. When HIGH, the outputs are active. When LOW, the true output is low and the compliment output is high. LVCMOS/LVTTL interface levels. Core supply pins. Pullup Pulldown Determines output divider value as defined in Table 3D, Function Table. LVCMOS/LVTTL interface levels. Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Differential output pair for the synthesizer. LVPECL interface levels. Output supply pin for FOUTA/nFOUTA LVPECL outputs. Differential output pair for the synthesizer. LVPECL interface levels. Output supply pin for FOUTB/nFOUTB LVPECL outputs. Reference clock output. LVCMOS/LVTTL interface levels. Output supply pin for REF_OUT. No internal connection. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to go high. When Logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS/LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
6
OEA
Input
Pullup
7 8, 14 9, 10 11 12, 24 13 15, 16 17 18, 19 20 21 22 23, 31, 32, 35, 36
OEB VCC NA0, NA1 NA2 VEE TEST FOUTA, nFOUTA VCCO_A FOUTB, nFOUTB VCCO_B REF_OUT VCCO_REF nc
Input Power Input Input Power Output Output Power Output Power Output Power Unused
Pullup
25
MR
Input
Pulldown
26
S_CLOCK
Input
Pulldown
continued on next page.
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ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Number 27 28 29 30 33, 34 37 38
Name S_DATA S_LOAD VCCA SEL XTAL_IN XTAL_OUT PCLK nPCLK Input Input Power Input
Type Pulldown Pulldown
Description Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. Analog supply pin. Selects between the crystal oscillator or the PCLK/nPCLK inputs as the PLL reference source. Selects XTAL inputs when LOW. Selects PCLK/nPCLK when HIGH. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Pulldown
Input Input Input Pulldown Pullup/ Pulldown Pulldown
Non-inverting differential clock input. Inverting differential clock input. VCC/2 default when left floating. Parallel load input. Determines when data present at M5:M0 is loaded into M divider, and when data present at NA2:NA0 and NB2:NB0 is loaded into the N output divider value. LVCMOS/LVTTL interface levels. Determines whether the synthesizer is in PLL or Bypass mode. LVCMOS/LVTTL interface levels. M divider integer inputs. The fractional portion of M divider can only be programmed by serial interface. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/LVTTL interface levels.
39
nP_LOAD
Input
40 41, 42, 43, 44, 45 46
VCO_SEL M0, M1, M2, M3, M4 M5
Input Input Input
Pullup Pulldown Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance REF_OUT Test Conditions Minimum Typical 4 51 51 7 Maximum Units pF k k
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Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs MR H L L L L L L L nP_LOAD X L H H H H H M X Data Data X X X X X N X Data Data X X X X X S_LOAD X X L L L H S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Conditions Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input does not affect shift registers. S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
Table 3B. Programmable VCO Frequency Function Table, P = /1
VCO Frequency (MHz) 500 * 550 * 625 32 M Divide 20 * 22 * 25 M5 0 * 0 * 0 16 M4 1 * 1 * 1 8 M3 0 * 0 * 1 4 M2 1 * 1 * 0 2 M1 0 * 1 * 0 1 M0 0 * 0 * 1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 25MHz.
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HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Table 3C. Programmable Pre Divider Function Table
Inputs P2 0 0 0 0 1 1 1 1 P1 0 0 1 1 0 0 1 1 P0 0 1 0 1 0 1 0 1 Pre Divider Value 1 (default) 2 4 8 16 32 5 25
Table 3D. Programmable Output Divider Function Table
Inputs N Divider Value Nx2 0 0 0 0 1 1 1 1 Nx1 0 0 1 1 0 0 1 1 Nx0 0 1 0 1 0 1 0 1 1 2 3 4 (default) 5 6 8 16 Minimum 490 245 163.33 122.5 98 81.67 61.25 30.625 Maximum 640 325 216.67 162.5 130 108.33 81.25 40.625 Output Frequency (MHz)
NOTE: "x" denotes Bank A or Bank B.
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, VO (LVCMOS) Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC + 0.5V 50mA 100mA -0.5V to VCCO_REF + 0.5V 65.7C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V5%, VCCO_A = VCCO_B = VCCO_REF = 3.3V5% or 2.5V5%, VEE =0V, TA = 0C to 70C
Symbol VCC VCCA VCCO_A, VCCO_B, VCCO_REF IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage 2.375 Power Supply Current Analog Supply Current 2.5 2.625 182 13 V mA mA Test Conditions Minimum 3.135 VCC - 0.13 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VCC 3.465 Units V V V
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Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V5%, VCCO_REF = 3.3V5% or 2.5V5%, VEE =0V, TA = 0C to 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage P[2:0], NB2, NA2, MR, OE_REF, SEL, M[4:0], S_CLOCK, S_DATA, S_LOAD, nP_LOAD M5, NA[1:0], NB[1:0], VCO_SEL, OEA, OEB P[2:0], NB2, NA2, MR, OE_REF, SEL, M[4:0], S_CLOCK, S_DATA, S_LOAD, nP_LOAD M5, NA[1:0], NB[1:0], VCO_SEL, OEA, OEB Output High Voltage REF_OUT; NOTE 1 TEST; NOTE 2 Output Low Voltage REF_OUT; NOTE 1 TEST; NOTE 2 Test Conditions VCC = 3.3V VCC = 3.3V Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 Units V V
IIH
Input High Current
VCC = VIN = 3.465V
150
A
VCC = VIN = 3.465V
5
A
IIL
Input Low Current
VCC = 3.465V, VIN = 0V
-5
A
VCC = 3.465V, VIN = 0V VCCO_REF = 3.3V% VCCO_REF = 2.5V5% VCC = 3.3V% VCCO_REF = 3.3V5% or 2.5V5% VCC = 3.3V%
-150 2.6 1.8 2.6 0.5 0.5
A V V V V V
VOH
VOL
NOTE 1: Output terminated with 50 to VCCO_REF/2. See Parameter Measurement Information section. Load Test Circuit diagrams. NOTE 2: Output terminated with 50 to VCC/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
Table 4C. LVPECL DC Characteristics, VCC =3.3V5%, VCCO_A = VCCO_B = 3.3V5% or 2.5V5%,VEE =0V, TA = 0C to 70C
Symbol IIH IIL VPP VCMR VOH VOL VSWING Parameter Input High Current Input Low Current nPCLK Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3 Peak-to-Peak Output Voltage Swing PCLK/nPCLK PCLK Test Conditions VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.3 VEE + 1.5 VCCO - 1.4 VCCO - 2.0 0.6 1.0 VCC VCCO - 0.9 VCCO - 1.7 1.0 Minimum Typical Maximum 150 Units A A A V V V V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 3: Outputs terminated with 50 to VCCO_A, _B - 2V.
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HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Table 5. Input Frequency Characteristics, TA = 0C to 70C
Symbol Parameter XTAL_IN, XTAL_OUT; NOTE 1 fIN Input Frequency Rise/Fall Time PCLK/nPCLK; NOTE 2 S_CLOCK tR / tF S_CLOCK, S_DATA, S_LOAD 6 Test Conditions Minimum 12 9 Typical Maximum 40 800 40 Units MHz MHz MHz ns
M = MINT + MCALC. The M value must be set for the VCO range to operate within the 490MHz - 650MHz range. When MFRAC = 0, set bits DS1=0 and DS0 = 0 NOTE 1: Using the minimum crystal input frequency of 12MHz, valid values of M are 40.8333 M 54.1667. This means that MINT has a range of 40 MINT 54 assuming the MFRAC is used to meet the requirement 40.8333 M 54.1667. When used, adjust MFRAC to adjust the value of M according to the instructions on page 3. Using the maximum crystal input frequency of 40MHz, valid values of M are 12.25 M 16.25. This means that MINT has a range of 12 MINT 16.25 assuming the MFRAC is used to meet the requirement 12.25 M 16.25. When used, adjust MFRAC to adjust the value of M according to the instructions on page 3. NOTE 2: Using the PCLK/nPCLK input frequency of 9MHz, when the pre-divider = 1, valid values of M are 54.4444 MINT 58. This means that MINT has a range of 54 MINT 58 assuming the MFRAC is used to meet the requirement 54.4444 M 58. MINT must not be set higher than 58. Using the PCLK/nPCLK input frequency of 50MHz, when the pre-divider = 1, valid values of M are 10 M 13. This means that MINT has a range of 10 MINT 13 assuming the MFRAC is used to meet the requirement 10 M 13. MINT must not be set lower than 10.
Table 6. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 12 Test Conditions Minimum Typical Fundamental 40 50 7 MHz Maximum Units
pF
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AC Electrical Characteristics
Table 7. AC Characteristics, VCC = VCCO_A = VCCO_B = VCCO_REF = 3.3V5% or 2.5V5%, VEE =0V, TA = 0C to 70C
Symbol fPD fVCO fOUT Parameter Phase Detector Input Frequency VCO Frequency Output Frequency VIN = 77.76MHz, VOUT = 155.52MHz, Integer Mode is N = /4 VIN = 77.76MHz, VOUT = 194.4MHz, Integer Mode is N = /3 VIN = 77.76MHz, VOUT = 161.1322MHz, Frac-N Mode is N = /4 VIN = 77.76MHz, VOUT = 173.3714MHz, Frac-M Mode is N = /3 VIN = 77.76MHz, VOUT = 155.52MHz, Integer Mode is N = /4 VIN = 77.76MHz, VOUT = 194.4MHz, Integer Mode is N = /3 VIN = 77.76MHz, VOUT = 161.1322MHz, Frac-N Mode is N = /4 VIN = 77.76MHz, VOUT = 173.3714MHz, Frac-M Mode is N = /3 tDJ tsk(o) tR / tF Deterministic Jitter Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle PLL Lock Time FOUTx/nFOUTx FOUTx/nFOUTx odc tLOCK FOUTx/nFOUTx FOUTx/nFOUTx 20% to 80% Output Divider = 1 Output Divider = 2 Output Divider 1, 2 200 40 43 46 Output Divider = 3, Mfrac = 0 Output Divider = 3, Mfrac 0 Test Conditions Minimum 9 490 30.625 Typical Maximum 50 650 640 60 Units MHz MHz MHz ps
130
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
100
ps
170
ps
8
ps
5
ps
tjit(per)
Period Jitter, RMS
18
ps
6 100 125 170 700 60 57 54 200
ps ps ps ps ps % % % ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: See Parameter Measurement Information section. NOTE 1:This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
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Parameter Measurement Information
2V 2V 2.8V0.04V 2V 2.8V0.04V
VCC, VCCO_A, VCCO_B VCCA
Qx
SCOPE
VCC VCCO_A, VCCO_B
Qx
VCCA
SCOPE
LVPECL
nQx
LVPECL
nQx VEE
VEE
-1.3V0.165V -0.5V0.125V
3.3/3.3V LVPECL Output Load AC Test Circuit
3.3V/2.5V LVPECL Output Load AC Test Circuit
2.05V5%
1.65V5% 1.65V5%
1.25V5% 2.05V5%
VCC, VCCO_REF VCCA
SCOPE
VCC,
SCOPE
VCCA
LVCMOS
GND
Qx
VCCO_REF
LVCMOS
GND
Qx
-1.65V5%
-1.25V5%
3.3/3.3V LVCMOS Output Load AC Test Circuit
3.3/2.5V LVCMOS Output Load AC Test Circuit
VCC
VOH VREF
nPCLK
V
PP
Cross Points
V
CMR
PCLK
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
VOL
VEE
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
Differential Input Level
Period Jitter
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Parameter Measurement Information, continued
nFOUTx nFOUTx FOUTx FOUTx
tcycle n
tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles
Cycle-to-Cycle Jitter
nFOUTx FOUTx nFOUTx
t PW
t
PERIOD
odc =
t PW t PERIOD
LVPECL Output Duty Cycle/Pulse Width/Period
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tcycle n+1
nFOUTy FOUTy
tsk(o)
LVPECL Output Skew
80%
80% VSW I N G
20%
FOUTx
20% tR tF
x 100%
LVPECL Output Rise/Fall Time
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Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8430002 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
Figure 2. Power Supply Filtering
Wiring the Differential Input to Accept Single-Ended Levels
Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
Figure 3. Single-Ended Signal Driving Differential Input
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Crystal Input Interface
The ICS8430002 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 4 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. These same capacitor values will tune any 18pF parallel resonant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p
Figure 4. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 5. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal.
VCC
VCC
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 5. General Diagram for LVCMOS Driver to XTAL Input Interface
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LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 6A to 6E show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V 3.3V R1 50 Zo = 50 PCLK Zo = 50 nPCLK R2 50
CML
LVPECL Input
LVPECL Input
Figure 6A. PCLK/nPCLK Input Driven by an Open Collector CML Driver
Figure 6B. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 PCLK Zo = 50 nPCLK R4 125
3.3V 3.3V 3.3V R3 84 Zo = 50 C1 PCLK Zo = 50 C2 nPCLK R4 84
3.3V LVPECL
LVPECL
R1 84 R2 84
LVPECL Input
R5 100 - 200
R6 100 - 200
R1 125
R2 125
LVPECL Input
Figure 6C. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver
Figure 6D. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple
2.5V 3.3V 2.5V R3 120 Zo = 60 PCLK Zo = 60 nPCLK R4 120
SSTL
R1 120 R2 120
LVPECL Input
Figure 6E. PCLK/nPCLK Input Driven by an SSTL Driver
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Recommendations for Unused Input and Output Pins Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground.
Outputs:
TEST Output
The unused TEST output can be left floating. There should be no trace attached.
LVCMOS Output
All unused LVCMOS output can be left floating. There should be no trace attached.
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground.
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 7A and 7B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 3.3V Zo = 50 + 3.3V
R3 125 Zo = 50
3.3V
R4 125
3.3V +
_ LVPECL Zo = 50 R1 50 RTT = 1 * Zo ((VOH + VOL) / (VCC - 2)) - 2 R2 50 VCC - 2V RTT Input LVPECL Zo = 50 R1 84 R2 84 _ Input
Figure 7A. 3.3V LVPECL Output Termination
Figure 7B. 3.3V LVPECL Output Termination
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Termination for 2.5V LVPECL Outputs
Figure 8A and Figure 8B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to ground level. The R3 in Figure 8B can be eliminated and the termination is shown in Figure 8C.
2.5V 2.5V 2.5V VCC = 2.5V R1 250 50 + 50 - - R3 250 50 + VCC = 2.5V
50
2.5V LVPECL Driver
R1 50 R2 50
2.5V LVPECL Driver
R2 62.5 R4 62.5
R3 18
Figure 8A. 2.5V LVPECL Driver Termination Example
Figure 8B. 2.5V LVPECL Driver Termination Example
2.5V VCC = 2.5V
50 +
50 -
2.5V LVPECL Driver
R1 50 R2 50
Figure 8C. 2.5V LVPECL Driver Termination Example
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Schematic Example
Figure 9 shows an example of ICS8430002 application schematic. In this example, the device is operated at VCC = VCCO = 3.3V. The device are be driven by a crystal, LVCMOS or LVPECL input sources. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. For the LVPECL output drivers, only two termination examples are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note.
VCC 3.3V Zo = 50 Ohm nFOUTB Zo = 50 Ohm LVPECL R10 50 R5 82.5 R6 82.5 Zo = 50 Ohm R11 50 R1 133 R2 133 Zo = 50 Ohm +
FOUTB
Driver_LVPECL
Optional Y-Termination
R12 50
VCC=3.3V VCCO=3.3V
U1
48 47 46 45 44 43 42 41 40 39 38 37
P1 P0 M5 M4 M3 M2 M1 M0 VCO_SEL
25MHz 18pF
VCC
TEST VCC FOUTA nFOUTA VCCO_A FOUTB nFOUTB VCCO_B REF_OUT VCCO_REF NC VEE
C5 0.1u
P2 NB0 NB1 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2
1 2 3 4 5 6 7 8 9 10 11 12
P1 P0 M5 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD nPCLK PCLK
X1
C1 27pF
P2 NB0 NB1 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2 VEE
nc nc X_OUT X_IN nc nc SEL VCCA S_LOAD S_DATA S_CLOCK MR
36 35 34 33 32 31 30 29 28 27 26 25
C2 27pF VCC SEL R9 VCCA C3 0.01u C4 10u 10
MR
VCCO
C8 0.1u
C9 0.1u C6 0.1u
VCC
FOUTB nFOUTB
13 14 15 16 17 18 19 20 21 22 23 24 VCCO C7 0.1u REF_OUT 3.3V
8430002
R13 33
Zo = 50 Ohm
Logic Control Input Examples
VCC
Set Logic Input to '1'
RU1 1K
VCC
Set Logic Input to '0'
RU2 Not Install
FOUTA
Zo = 50 Ohm
R3 133
R4 133
LVCMOS
+
RD1 Not Install
To Logic Input pins
RD2 1K
To Logic Input pins
nFOUTA
Zo = 50 Ohm
-
R7 82.5
R8 82.5
Figure 9. ICS8430002 Schematic Example
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8430002. Equations and example calculations are also provided. 1. Power Dissipation.
The total power dissipation for the ICS8430002 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 182mA = 630.63mW Power (LVPECL outputs)MAX = 30mW/Loaded Output pair Power (LVPECL output) = 2 * 30mW = 60mW
LVCMOS Output Power Dissipation * * Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 7)] = 30.4mA Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 7 * (30.4mA)2 = 6.47mW per output
Total Power Dissipation * Total Power = Power (core) + Power (LVPECL output) + Power (ROUT) = 630.63mW + 60mW + 6.47mW = 697.1mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 65.7C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.697W * 65.7C/W = 115.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board.
Table 8. Thermal Resistance JA for 48 Lead TQFP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 65.7C/W 1 55.9C/W 2.5 52.4C/W
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3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 10.
VCCO
Q1
VOUT
RL 50
VCCO - 2V
Figure 10. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO - 2V. * * For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 9. JA vs. Air Flow Table for a 48 Lead LQFP
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 65.7C/W 1 55.9C/W 2.5 52.4C/W
Transistor Count
The transistor count for ICS8430002 is: 7495
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Package Outline and Package Dimensions
Package Outline - Y Suffix for 48 Lead LQFP
Table 10. Package Dimensions for 48 Lead LQFP
JEDEC Variation: BBC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 48 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.50 Ref. e 0.5 Basic L 0.45 0.60 0.75 0 7 ccc 0.08 Reference Document: JEDEC Publication 95, MS-026
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Ordering Information
Table 11. Ordering Information
Part/Order Number 8430002AYLF 8430002AYLFT Marking ICS8430002AL ICS8430002AL Package "Lead-Free" 48 Lead LQFP "Lead-Free" 48 Lead LQFP Shipping Packaging Tray 1000 Tape & Reel Temperature 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev B Table T1 Page 5 2 4 5 8 11 1 Description of Change Pin 5, 6, 7 added to descriptions. Changed max VCO from 640MHz to 650MHz throughout the datasheet. Block Diagram - changed OE_A, OE_B to OEA, OEB. Figure 1, Parallel & Serial Load Operations - correct M[11:0] to M[5:0]. Pin Descriptions Table - changed OE_A, OE_B to OEA, OEB. Programmable Output Divider Table - corrected Output Frequency max. column. Input Frequency Characteristics - corrected equations in NOTE 1 and NOTE 2. General Description - deleted the word possible at the end of the first sentence. Date 5/5/09
C
T1 T3D T5
8/24/09
C
11/12/09
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Technical Support netcom@idt.com +480-763-2056
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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